The present invention relates to a data pattern synchronizer for providing synchronization with an input data pattern in an apparatus which measures a transmission error rate of a digital transmission system.
The transmission error rate of a digital transmission system is usually measured in such a manner as described below. At the input side of the digital transmission system to be measured, a data pattern for measurement, which is a recurrence of a fixed pattern of a predetermined bit length, is obtained from a data pattern generator and is then supplied to the digital transmission system. At the output side of the digital transmission system, a reference, data pattern similar to the data pattern applied to the digital transmission system is obtained from a data pattern generator similar to that at the input side. The reference data pattern is compared, on a bitwise basis, with the data pattern transmitted over the digital transmission system and having developed errors by the transmission, by which the errors of the transmitted data pattern are detected, and the number of such errors per unit bit length is counted.
In this instance, if the reference data pattern available from the data pattern generator at the output side of the digital transmission system is not synchronized with the input data pattern transmitted over the transmission system, it would be determined that the input data pattern has an error, even if the data is error-free. To avoid this, the reference data pattern generator is provided in association with a data pattern synchronizer for synchronizing the reference data pattern with the input data pattern, and errors of the input data pattern are counted in a state in which the reference data pattern is held in synchronism with the input data pattern.
Conventionally, the data pattern synchronizer for such an error rate measuring apparatus has such an arrangement as shown in FIG. 1. An input data pattern Di containing errors, transmitted over the digital transmission system, is provided via an input terminal 11 to a data comparator 22 which forms a data disagreement detector 21. A clock regenerator 24 regenerates, in synchronism with the input data pattern Di, a clock Co of frequency equal to its bit rate. The clock Co is applied to an AND gate 25 and its output clock Cg is provided to a data pattern generator 26, from which a reference data pattern Dr of exactly the same contents as the original contents of the input data pattern is obtained bit by bit for each pulse of the clock Cg. The reference data pattern Dr is supplied to the data comparator 22.
The data comparator 22 compares the input data pattern Di and the reference data pattern Dr on a bitwise basis and yields a data disagreement detection signal Sd of an NRZ waveform which goes low-level or high-level depending on whether the both data patterns agree with each other or not. The detection signal Sd is applied to an AND gate 23, which is also supplied with the clock Co from the clock regenerator 24. The AND gate 23, that is, the data disagreement detector 21 yields a data disagreement detection pulse Pe of the same pulse width as that of the clock Co when the input data pattern Di and the reference data pattern Dr do not agree with each other.
The data disagreement detection pulse Pe is provided to an output terminal 12. The clock Co from the clock regenerator 24 is supplied to a 1/k-frequency divider 31 (where k is a positive integer), in which it is frequency divided down to 1/k and from which a positive output pulse Pk is provided every k periods of the clock Co. The output pulse Pk is applied to an OR gate 27 and its output pulse Po is applied to a reset terminal R of a 1/l-frequency divider 28, resetting it every k periods of the clock Co. On the other hand, the data disagreement detection pulse Pe is applied to and frequency divided by the frequency divider 28 down to 1/l (where l is a positive integer smaller than k). When l shots of data disagreement detection pulses Pe have been produced within the k periods of the clock Co as a result, it is determined that the reference data pattern Dr is not synchronized with the input data pattern Di, and the frequency divider 28 yields an output pulse Pl. That is to say, it is presumed that the transmission error rate of the digital transmission system will not exceed a rate l/k, and when the rate of detected errors which are provided to the output terminal 12 exceeds the rate l/k, it is determined that the reference data pattern Dr is not synchronized with the input data pattern Di.
The output pulse Pl of the frequency divider 28 is applied to an inhibit pulse generator 29, from which a positive inhibit pulse Pi is generated. The inhibit pulse Pi is inverted and then applied to the AND gate 25 to inhibit the supply of the clock Co to the data pattern generator 26 for a period of the pulse width .tau..sub.D of the inhibit pulse Pi, and consequently, the generation of the reference data pattern from the data pattern generator 26 is stopped for the period .tau..sub.D. At the same time, the inhibit pulse Pi from the inhibit pulse generator 29 is applied to a reset terminal R of the frequency divider 31 and the OR gate 27, resetting the frequency dividers 31 and 28 when the supply of the clock Co to the data pattern generator 26 is inhibited.
In this way, the supply of the clock Co to the data pattern generator 26 is inhibited for the period .tau..sub.D, during which the generation of the reference data pattern Dr from the data pattern generator 26 is suspended. By this, the phase of the reference data pattern Dr available from the data pattern generator 26 is delayed by the number of inhibited pulses of the clock Co, and such a phase correction is repeated upon each generation of the inhibit pulse Pi from the inhibit pulse generator 29, by which the reference data pattern Dr is synchronized with the input data pattern Di.
However, if the number of pulses of the clock Co which are inhibited by the inhibit pulse Pi, that is, the number of bits by which the reference data pattern Dr is delayed for each phase correction, is fixed to a specific number, the reference data pattern Dr may not be synchronized with the input data pattern Di in some cases. Consider, for example, the case where the data pattern is a PN pattern 2.sup.4 -1 which is a recurrence of a 15-bit pattern and the reference data pattern Dr is delayed three bits by each phase correction. When the reference data pattern Dr initially leads the input data pattern Di by two bits as indicated by STATE 1 in FIG. 2 in which data of the 15-bit pattern are represented by A, B, C, . . . O, the reference data pattern Dr will be put out of phase with the input data pattern Di, by individual phase corrections, as indicated by STATE 2, 3, 4, 5, 1, . . . in FIG. 2. No matter how many times the phase correction may be effected, the reference data pattern Dr will not be synchronized with the input data pattern Di. To avoid this, provision must be made so that the number of pulses of the clock Co which are inhibited by each inhibit pulse Pi will not be prime factors of the data pattern length nor will it be their integral multiples. Alternatively, the inhibit pulse generator 29 may be arranged so that the pulse width .tau..sub.D of the inhibit pulse Pi is modulated randomly within a range larger than one period of the clock Co.
At any rate, according to the above-described conventional data pattern synchronizer, the inhibit pulse generator 29 does not yield the inhibit pulse Pi until l data disagreement detection pulses Pe are counted in the frequency divider 28, and consequently, the cycle period of phase correction of the reference data pattern Dr is long. In other words, the prior art synchronizer consumes much time for synchronizing the reference data pattern Dr with the input data pattern Di. In addition, the random modulation of the pulse width of the inhibit pulse Pi will bring about random changes in the number of bits by which the reference data pattern Dr is delayed for each phase correction, and hence it is difficult to predict how many times the phase correction must be effected to establish synchronization. Furthermore, the additional provision of a special circuit to the inhibit pulse generator 29 for randomly modulating the pulse width of the inhibit pulse Pi will introduce complexity in the circuit arrangement of the synchronizer.